1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device. More specifically, the invention relates to a test technique which is effective when a chip batch writing and erasing test is carried out in an EEPROM flash memory capable of electrically erasing and writing data.
2. Description of the Related Background Art
At present, as nonvolatile semiconductor memory devices, EEPROM flash memories capable of electrically writing/erasing data are known. As memory cells of such flash memories, stacked gate type memory cells are put to practical use. Such a memory cell comprises a floating gate of a polysilicon material, which is formed on a semiconductor substrate via a tunnel oxide film having a thickness of about 9 nm, and a control gate of a polysilicon material, which is formed on the floating gate via an intergate insulating film.
As EEPROM flash memories, there have been developed NOR type EEPROM flash memories which have a plurality of memory cells connected to bit lines in parallel, AND type and DINOR type EEPROM flash memories as modifications thereof, NAND type EEPROM flash memories using a basic unit which has a plurality of memory cells connected in series. Among these memories, the NAND type flash memories are widely noticed since these memories can be high-density-integrated.
In order to test the memory cells of a NAND type flash memory for defects, a test system for batch writing and erasing all of memory cells is used. The batch writing test is a test for injecting electrons into the floating gates of all of memory cells to set a high threshold by supplying a high writing voltage VPPW to all of control gate lines and by supplying a ground (Vss) voltage to the p-type well of the cell array region. This batch writing test can be realized if a pre-decoder circuit for row addresses is formed so as to multi-select row addresses and if the circuit is formed so as to supply VPPW from all of 16 global control line voltage supply circuits in the case of 16 NANDs.
In addition, the batch erasing test is a test for extracting electrons from the floating gates of all of memory cells to set a low threshold by supplying Vss to the control gate lines of all of the memory cells and by supplying a high erasing voltage VPPE to the p-type well of the cell array. Similar to the batch writing test, the batch erasing test can be realized if a pre-decoder circuit for row addresses is formed so as to multi-select row addresses during batch erasing and if an erasing operation is carried out while all of blocks are set to be in a selected state.
However, when the above described batch writing test or batch erasing test is carried out, if a memory cell is defective, a high voltage supplied from a booster circuit leaks to cause a problem that the output voltage of the booster circuit falls. FIGS. 18A and 18B, respectively, are a sectional view and equivalent circuit diagram showing the state of defects in a NAND type memory cell. In FIGS. 18A and 18B, reference numbers (1) through (6) denote defects which may be caused in an actual producing process. Reference number (1) denotes a defective model when a bit line BL being a metal wiring and a select gate line SGD of a polysilicon material are electrically short-circuited by contaminants or the like. Reference numbers (2) and (5) denote defective models when a gate oxide film of a select gate SG is broken to electrically establish a short circuit between a select gate line SGD or SGS and a substrate. Reference number (3) denotes a defective model when a bit line BL and a control gate line CG of a polysilicon material are electrically short-circuited by contaminants or the like. Reference number (4) denotes a defective model when thin oxide films between a control gate CG and floating gate FG of a memory cell and between the floating gate FG and a substrate are broken to electrically establish a short circuit between the control gate CG and the substrate. Reference number (6) denotes a defective model when a source-side select gate line SGS and a source diffusion layer line are electrically short-circuited by contaminants or the like.
Among these defective models, the short circuit between the control gate CG and the substrate in (4) is caused if an intergate insulating film (usually, an ONO film) between the control gate CG and the floating gate FG is defective. If the ONO film of a defective cell is defective in the producing stage and if the control gate CG and floating gate FG of the memory cell have the same potential, a higher writing voltage than a withstand voltage of a tunnel oxide film of the memory cell is applied to the tunnel oxide film during the writing test, so that the tunnel oxide film of the defective memory cell is instantly broken. In addition, if the floating gate FG and the substrate are short-circuited by defects of the tunnel oxide film of a certain memory cell, a higher voltage than the withstand voltage is applied to the ONO film, so that the ONO film is instantly broken.
If such a defective memory cell exists, the boosted voltage of the control gate line leaks in the substrate to fall during the batch writing test. Therefore, the voltages of normal control gate lines, to which no defective memory cells are connected, also fall from a predetermined VPPW. In addition, during the batch erasing test, there is a problem in that the boosted voltage of the p-type well leaks in the control gate line, so that the boosted voltage VPPE falls. Also, in the case of (3) wherein the control gate line and the bit line are short-circuited, there is a problem in that the boosted voltages VPPW and VPPE fall during the batch writing and batch erasing operations, respectively.
Therefore, it is not conventionally possible to carry out the batch writing test and the batch erasing test unless the substitution of a redundant cell array for the defective memory cell is completed. FIG. 19 shows the flow of a conventional test operation until assembly after a wafer sorting test for a NAND type flash memory or the like. First, in order to find the address of a defective memory cell, a writing operation every page and an erasing operation every block are carried out (step S1). On the basis of the result thereof, the defective address of a defective memory cell is stored in each of memory chips. For example, there is often used means for storing the defective address by a fuse programming for cutting a fuse element of, e.g., a polysilicon material, by means of a laser (step S2).
Thereafter, in order to screen initial defectives out, the batch writing test and the batch erasing test are carried out predetermined times, and a writing/erasing stress is applied to the memory cell. After the stress is applied, the final writing/erasing test is carried out to select non-defectives (step S3). Then, only selected non-defectives are assembled (step S4). If the oxide film of the memory cell is deteriorated by the writing/erasing stress and if the number of defective bits increases after the batch writing/erasing test, this chip is discarded as a defective. Therefore, if the oxide film of the memory cell is greatly deteriorated by the writing/erasing test, the number of obtained non-defectives decreases, so that there is a problem in that the cost of producing chips increases. In addition, in order to prevent the chip from being discarded to decrease the yields, there is a method for cutting a fuse element at an address which is defective again. However, it is required to cut the fuse element twice by means of the laser, so that there is a problem in that the testing time and the testing costs increase.
As described above, in order to carry out the batch writing or batch erasing test with respect to conventional NAND type flash memories, it is required to prevent the applied high voltage from falling due to the defective memory cell, so that the redundant cell must be substituted for the defective memory cell. This increases the cost of producing flash memories.
The same problem is caused in EEPROMs of types other than NAND type EEPROMs.